Tuning CPU resources

• Math coprocessors perform floating point calculations much more efficiently than software can. The 80486DX, 80486DX2, 80486DX4, and Pentium include floating-point capability on the chip itself. Without a floating point coprocessor, the CPU must emulate it using software -- this is considerably slower. On systems with an SCO^® SMP^® License, you can use the -F option to mpsar(ADM) to monitor how many processes are using floating point arithmetic. This command displays information about the usage of both floating point hardware and software emulation.

• Direct memory access (DMA) controllers handle memory transfer between devices and memory, or memory and memory. Many hardware peripheral controllers on EISA and MCA bus machines have a built-in Bus Master DMA chip that can perform DMA rather than relying on the DMA controller on the motherboard. On MCA bus machines, a chip called a Central Arbitration Control Point (CACP) decides which Bus Master DMA controller gets control of the bus.

  An important limitation of all DMA controllers on ISA and early-series MCA bus machines, and some peripheral controllers on all bus architectures, is that they cannot address more than the first 16MB of memory (24-bit addressing). When the operating system encounters hardware with such limitations, it must instruct the CPU to transfer data between the first 16MB and higher memory.

  Some peripheral controllers (including IDE disk controllers) and older SCSI host adapters either cannot perform DMA or the device driver may not support its use. In this case, the operating system instructs the CPU to transfer data between the peripheral and memory on behalf of the hardware. This is known as programmed I/O (PIO).

• Graphics adapters that can take advantage of a local bus architecture (such as VL Bus or PCI) operating at the same speed as the CPU produce a substantial improvement in the performance of the graphics subsystem.

• Universal asynchronous receiver/transmitters (UARTs) control input and output (I/O) on serial lines. Buffering on UARTs enables more efficient use of the CPU in processing characters input or output over serial lines.

  Intelligent serial cards are able to offload much of the character processing that the CPU might otherwise have to perform.

• Programmable interrupt controllers (PICs) handle interrupts from hardware peripheral devices when they are trying to get the attention of the CPU.